Electrostatic Discharge (ESD) protection is a critical problem for modern integrated circuits. With a low breakdown voltage of transistors in submicron processes, it is important to provide a method of protecting power supply pins from ESD damage, especially on smaller chips where there is no high capacitance available to absorb current from a discharge. On many circuits a method used to provide this protection is a shunt circuit that responds to a rapid rise of voltage on a power supply line by shunting a power supply line to ground during an ESD upset event.
It is possible to distinguish between an ESD event and a normal application of power by a difference in rise time. During an ESD event a rise time on a power supply line is in the range of 10 nanoseconds (ns), whereas a rise time during regular application of power to the supply line is in most of cases typically much greater than 1 microsecond (μs) but may be, in some extreme cases, in the range of hundreds of nanoseconds. However, in extreme cases during normal operation, when several outputs switch simultaneously, it is possible that a voltage drop due to noise (due to either an IR or RLC voltage drop) on a power supply line can reach a nanosecond time range and trigger a threshold voltage of some protective devices. Additionally, conventional ESD trigger circuits have a constraint that they also need to remain on for several microseconds to be effective during an ESD upset. In extremely noisy power supply situations, it is possible to generate a false triggering of a shunt circuit.
With reference to FIG. 1, a series configuration of a trigger capacitor 115 and a trigger resistor 120 connects between VDD 105 and ground 110 in a first prior art ESD shunt circuit 100. An ESD inverter 130 and a trigger inverter 140 each connect between VDD 105 and ground 110. An ESD trigger line 125 connects between a series connection node (between the trigger capacitor 115 and the trigger resistor 120) and an input of the ESD inverter 130. A trigger line 135 connects between an output of the ESD inverter 130 and an input of the trigger inverter 140. An ESD shunt device 145 connects between VDD 105 and ground 110. An ESD shunt trigger line 150 connects between an output of the trigger inverter 140 and an input of the ESD shunt device 145.
In FIG. 1, the first prior art ESD shunt circuit 100 makes use of an RC time constant produced by a series configuration of the trigger capacitor 115 and the trigger resistor 120. An RC time constant is selected away from (i.e., shorter than) a magnitude of a rise time expected on a power supply node VDD 105. However, a RC time constant should also be sufficiently long to provide full dissipation of a charge build up from an ESD event prior to turning off a shunt. A time required to discharge the ESD event is dependent on a time constant determined by a discharging network and a RC time constant of the trigger device. To be effective, a time constant must also be long enough to keep a shunt enabled for the duration of the ESD upset event. Using some typical values from a human body model (HBM) standard, 5000 volts (V), 100 picoFarads (pF), and 1500 Ohms produce the ESD upset event with a discharge time of approximately 1 microsecond being required to discharge a VDD 105 line to a level <5 V. Therefore, a value of an internal RC time constant would need to be >2 microseconds to ensure that the ESD shunt device 145 remains enabled for 1 microsecond. As previously stated, this time constant is long enough to be easily achieved by a noisy power bus or a rapid power on. Therefore, the first prior art ESD shunt circuit 100 sufferers from a sensitivity to noise on VDD 105, a requirement to be used in situations where a power-on voltage ramp rate is low, and the amount of area to provide the large RC time constant is large.
With reference to FIG. 2, a series configuration of a trigger capacitor 215 and a trigger resistor 220 connects between VDD 205 and ground 210 in a second prior art ESD shunt circuit 200. An ESD inverter 230 and a trigger latch 240 each connect between VDD 205 and ground 210. An ESD trigger line 225 connects between a series connection node (between the trigger capacitor 215 and the trigger resistor 220) and an input of the ESD inverter 230. A trigger line 235 connects between an output of the ESD inverter 230 and an input of the trigger latch 240. An ESD shunt device 245 connects between VDD 205 and ground 210. An ESD shunt trigger line 250 connects between an output of the trigger latch 240 and an input of the ESD shunt device 245.
The second ESD shunt circuit 200 also uses an RC time constant to trigger the ESD shunt device 245, but uses the trigger latch 240 to maintain a triggered state of the ESD shunt device 245. By separating the ESD trigger elements (i.e., the trigger capacitor 215, the trigger resistor 220, and the ESD inverter 230) from an element sustaining the ESD trigger state (i.e., the trigger latch 240), a RC time constant for triggering can be reduced by a factor of 100. The first benefit of a reduction in a RC time constant is the surface saved. Reduction of a RC time constant eliminates also risk of an accidental trigger during a rapid (in the range of hundreds of nanoseconds) power-on of a system. An additional benefit of a reduction in a RC time constant, is less risk of false triggering during switching, which produces noise (on a order of nanoseconds) on VDD 205, caused by simultaneously switching outputs (SSO).
Since the risk of false triggering is less but not eliminated, the second ESD shunt circuit 200 can require additional timeout circuitry (not shown) which produces a release of the trigger latch 240 after a few microseconds delay typically. A timeout circuit is required to release the trigger latch 240 in cases where false triggering has occurred due to RLC noise or IR drop caused by SSO.